The present invention relates to semiconductor memory devices, and more particularly, to sense amplifier drive circuits for semiconductor memory devices.
Various random access semiconductor (integrated circuit) memory devices may be characterized as a static random access memory (SRAM) or a dynamic random access memory (DRAM). A memory cell of a DRAM may be fabricated more easily than a memory cell of a SRAM, which may be particularly beneficial in the manufacture of increasingly dense and reduced size semiconductor memory devices. To improve the reading and writing speed of data from a DRAM, the DRAM may be operated synchronously to a system clock of a circuit including the DRAM, such as provided by a circuit board on which the DRAM is mounted.
Such a random access memory device operating synchronously to the system clock is generally referred to as a S-DRAM(Synchronous Dynamic Random Access Memory). An S-DRAM typically synchronizes to the system clock to provide a reference in initiating various operations, such as data read/write operations. Various commands related to performance of functions of the S-DRAM are also generally input and output synchronously to the system clock. The input/output operations may, for example, be performed responsive to a leading edge or a trailing edge of the system clock, depending on the design of the S-DRAM.
For an S-DRAM, external signals applied from outside of the S-DRAM chip typically synchronize to the system clock. However, internal circuit(s) can be divided into a synchronous part, operating synchronous to the external clock, and an asynchronous part. The synchronous part may be further subdivided into a portion synchronizing to an external system clock applied from outside the DRAM and a portion synchronizing to an internal clock generated internal to the DRAM. For example, row address decoding, activation of a selected word line, bit line sensing and the like generally do not synchronize to the external system clock. Data input/output operations of the DRAM are generally synchronized to the external system clock.
FIG. 1 schematically illustrates the layout of a typical semiconductor memory device. A typical semiconductor memory device has a plurality of bit cells, such as memory cells, and a plurality of sense amplifiers for sensing and amplifying data through bit lines that are connected to the bit cells in a read operation. The sense amplifiers are generally driven by a sense amplifier driver circuit, which receives external clock signals and generates a sense amplifier-driving signal. As shown in FIG. 1, the semiconductor memory device includes four banks A, B, C, D (10, 12, 14, 16) that are arrayed in column and row relationship. Each of the memory banks A, B, C, D (10, 12, 14, 16) contains memory cells that are arrayed in column and row relationship. The memory cells store data, which may take a logic state of ‘1’ or ‘0’. A row decoder 20 is disposed between the bank A 10 and the bank B 12 on the same row and a row decoder 22 is disposed between the bank C 14 and the bank D 16, which share a common row, different from the row of banks A, B 10, 12. It is to be understood that a number of rows within a memory bank will generally be associated with each row of memory banks.
Column decoders 24, 28 are positioned opposite each other between the bank A 10 and the bank C 14 on the same column. The column decoders 24, 28 generally contain a plurality of decoders. Similarly, the column decoders 26, 30 are positioned opposite each other between the bank B 12 and the bank D 16 on a shared column, different from the column of the column decoders 24, 28. As with the rows, it is to be understood that a number of columns within a memory bank will generally be associated with each column of memory banks.
An input/output buffer and peripheral circuit 18 is disposed between the column decoders 24, 28 and also between the column decoders 26, 30. For the semiconductor memory device illustrated in FIG. 1, the four memory banks A, B, C, D (10, 12, 14, 16) constitute one bank group. An intermediate control circuit 21 is positioned between the memory bank groups 100, 200 and the memory bank groups 300, 400. The intermediate control circuit 21 may include, for example, a clock signal generator that generates various internal clock signals.
FIG. 2 is a schematic block diagram illustration of the layout of a semiconductor memory device, such as illustrated in FIG. 1, including various details related to driving an input/output sense amplifier. As with FIG. 1, four memory banks A, B, C, D (10, 12, 14, 16) are illustrated arrayed in column and row relationship. A row decoder 20 is positioned between the bank A 10 and the bank B 12 on the same memory bank row and a row decoder 22 is positioned between the bank C 14 and the bank D 16 on another common memory bank row. Column decoders 24, 28 are positioned opposite to each other between the bank A 10 and the bank C 14 on the same memory bank column and column decoders 26, 30 are positioned opposite to each other between the bank B 12 and the bank D 16 on another common memory bank column.
FIG. 2 further illustrates an array including an input/output sense amplifier 32 and a data multiplexer(MUX) 36 that may be formed as two layers and be separately disposed between the column decoders 24, 28. Also shown in FIG. 2 are an input/output sense amplifier 34 and a data MUX 38 that may be provided as two layers respectively arrayed between the column decoders 26, 30.
The circuit of FIG. 2 also shows: a column predecoding enable signal generator 40 that receives an external clock signal and a command decoding signal and generates a column predecoding enable signal; an input/output sense amplifier drive 42 that generates an input/output sense amplifier drive signal FRP(First Read Pulse); and a column predecoder 44 that receives the column predecoding enable signal and predecodes the signal. These circuits may be included, for example, in the intermediate control circuit 21.
FIG. 3 is a schematic block diagram illustration of a semiconductor memory device illustrating further aspects of driving the input/output sense amplifiers illustrated in FIG. 2. As illustrated in FIG. 3, to drive the input/output sense amplifiers of FIG. 2, a clock buffer 35 is provided for receiving, buffering and outputting an external clock. A command buffer 37 receives, buffers and outputs a read command READ_CMD. A command decoder 39 receives, decodes and outputs the read command output from the command buffer 37. A column predecoding enable signal generator 40 receives the external clock signal output from the clock buffer 35 and a command decoding signal decoded by the command decoder 39, and generates a column predecoding enable signal PDCAE. A column predecoder 44 receives the column predecoding enable signal PDCAE output from the column predecoding enable signal generator 40 and predecodes a column address. The column decoders 24, 26, 28, 30 receive and decode the column addresses PDCAi predecoded by the column predecoder 44 and output bit line selection signal(s) CSL(Column Select Line). An input/output sense amplifier drive 42 receives the column predecoding enable signal PDCAE output from the column predecoding enable signal generator 40 and generates and outputs an input/output sense amplifier drive signal FRP(First Read Pulse). The data MUXs 36, 38 receive the bit line selection signal(s) CSL output from the column decoders 24, 26, 28, 30 and selectively output data. The input/output sense amplifiers 32, 34 sense(amplify) and output the data selectively output from the data MUXs 36, 38 responsive to the input/output sense amplifier drive signal FRP output from the input/output sense amplifier drive 42. The data output buffer 46 buffers and outputs the data sensed by the input/output sense amplifiers 32, 34.
FIG. 4 is a timing diagram illustrating operations related to driving the input/output sense amplifiers of FIG. 3. The conventional operations for generating the input/output sense amplifier drive signal FRP and outputting data will now be described with reference to FIGS. 3 and 4. The clock buffer 35 receives and buffers the external clock and outputs an external clock signal E_CLK, as shown in FIG. 4 at row (A), to the column predecoding enable signal generator 40. The command buffer 37 receives, buffers and outputs the read command READ_CMD, as shown in FIG. 4 at row (B), to the command decoder 39. The command decoder 39 decodes the read command and applies it to the column predecoding enable signal generator 40. The column predecoding enable signal generator 40 receives the external clock signal E_CLK from the clock buffer 35 and the command decoding signal decoded by the command decoder 39 and generates the column predecoding enable signal PDCAE, shown in FIG. 4 at row (C). The signal PDCAE is applied to the column predecoder 44 and the input/output sense amplifier drive 42, as shown by the two dotted lines extending from the leading edge of the PDCAE signal as illustrated at row (C).
The column predecoder 44 receives the column predecoding enable signal PDCAE from the column predecoding enable signal generator 40, predecodes the column address, and applies the predecoded column addresse(s) PDCAi, as shown in FIG. 4 at row (D), to the column decoders 24, 26, 28, 30. The column decoders 24, 26, 28, 30 receive and decode the predecoded column addresses PDCAi from the column predecoder 44 and apply the bit line selection signal(s) CSL as shown in FIG. 4 at row (E), to the data MUXs 36, 38.
The input/output sense amplifier drive 42 receives the column predecoding enable signal PDCAE from the column predecoding enable signal generator 40 and generates the input/output sense amplifier drive signal(s) FRP(First Read Pulse), as shown in FIG. 4 at row (F). FRP is applied to each of the input/output sense amplifiers 32, 34. The input/output sense amplifiers 32, 34 sense the data selectively output (addressed) from the data MUXs 36, 38 individually in response to the input/output sense amplifier drive signals FRP from the input/output sense amplifier drive 42. The sensed (amplified) data is provided to the data output buffer 46. The data output buffer 46 buffers and outputs the data sensed by the input/output sense amplifier 32, 34.
For the conventional operations described with reference to FIGS. 3 and 4, when reading data, the input/output sense amplifiers 32, 34 are generally not driven unless data is already loaded on a secondary data line(s) from a memory cell that is selectively connected to the input/output sense amplifiers 32, 34 through input/output lines after generation of the bit line selection signal CSL (i.e., after selection/addressing of the cell). In addition, different signal paths are provided to receive the read command and generate the bit line selection signal CSL and to receive the read command and generate the input/output sense amplifier drive signal FRP. As a result, a delay time interval between the bit line selection signal CSL and the input/output sense amplifier drive signal FRP generally cannot be uniformly maintained. This may cause a corresponding delay margin to be varied and may result in signal skew.
Moreover, as the input/output sense amplifier drive 42 is generally located in the intermediate control circuit 21, the routing length of the input/output sense amplifier drive signal FRP between the input/output sense amplifier drive 42 and the input/output sense amplifiers 32, 34 may be lengthened. Such a lengthened routing length of the input/output sense amplifier drive signal FRP may cause a speed delay and/or increased consumption of power if repeaters are used in the routing, so that toggling may not be executed effectively at high frequencies.